A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. In a typical computer system, one or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. With many peripheral devices, such as graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate.
Much of a computer system's functionality and usefulness to a user is derived from the functionality of the peripheral devices. For example, the speed and responsiveness of the graphics adapter is a major factor in a computer system's usefulness as an entertainment device. Or, for example, the speed with which video files can be retrieved from a hard drive and played by the graphics adapter determines the computer system's usefulness as a training aid. Hence, the rate at which data can be transferred among the various peripheral devices often determines whether the computer system is suited for a particular purpose. The electronics industry has, over time, developed several types of bus architectures. Recently, the PCI (peripheral component interconnect) bus architecture has become one of the most widely used, widely supported bus architectures in the industry. The PCI bus was developed to provide a high speed, low latency bus architecture from which a large variety of systems could be developed.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory bus 110, respectively. A PCI bus 112 is coupled to each of PCI agents 114, 116, 118, 120, 122, 124 respectively, and is coupled to arbiter 106.
Referring still to Prior Art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, for example, interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. The PCI agent requesting ownership is referred to as an "initiator", or bus master. Upon being granted ownership of PCI bus 112 from arbiter 106, the initiator (e.g., PCI agent 116) carries out its respective data transfer.
Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates it transaction (e.g., data transfer) with a "target" or slave device (e.g., main memory 104). When the data transaction is complete, the PCI agent relinquishes ownership of the PCI bus, allowing arbiter 106 to reassign PCI bus 112 to another requesting PCI agent.
Thus, only one data transaction can take place on a PCI bus at any given time. In order to maximize the efficiency and data transfer bandwidth of PCI bus 112, PCI agents 114-124 follow a definitive set of protocols and rules. These protocols are designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112, so as to maximize its data transfer bandwidth. The PCI bus protocols and specifications are set forth in an industry standard PCI specification (e.g., PCI Specification - Revision 2.1). Where each of PCI agents 114-124 are high performance, well designed devices, data transfer rates of up to 528 Mbytes per second can be achieved (e.g., PCI bus 112 operating at 66 MHz).
There is a problem, however, when PCI bus architecture 100, as is often the case, includes PCI agents which are slower than others. Where one of PCI agents is much slower than the other PCI agents, this slowest PCI agent can potentially monopolize PCI bus 112, greatly harming the total data transfer bandwidth. For example, PCI agent 118 is an ISA (industry standard architecture) bus bridge. PCI agent 118 is thus much slower than the other PCI agents. Since the ISA bus runs much slower than the PCI bus and other peripheral devices coupled to the ISA bus can be slower still, PCI agent 118 can have a very slow access time. This causes an initiator (e.g., PCI agent 122) to wait for access, potentially tying up PCI bus 112 in the process.
In addition, it should be noted that there may be other reasons a target may have a slow access time. For example, the target may be busy with some internal activity and is unable to service the access at that time, or the access would generate some sort of internal conflict (e.g., with data ordering or coherency). Hence, to avoid monopolization problems, the PCI specification dictates that a target should issue a "retry" if its latency will exceed 16 PCI clock cycles. Accordingly, where a target "knows" it will be slow completing an access, it may issue a retry in order to free up the PCI bus for other initiators.
Prior Art FIG. 2 shows a diagram of a prior art access process 200. Process 200 is an access by a fast initiator PCI agent to a slow target PCI agent. The initiator PCI agent has a high data transfer rate (e.g., PCI agent 122) and the target PCI agent is a device having a slow data transfer rate and a high latency (e.g., PCI agent 118). On the left side of process 200, the initiator attempts to access the target, shown as the initial access. The initial access is comprised of the normal stages of a PCI data transaction (e.g., arbitration for bus ownership, receiving a grant signal from the arbiter, and the like). The initial access addresses and informs the target of the data to be transferred. The target, as described above, is an ISA bus bridge having a high latency period. In this example, the target has a latency of 16 PCI clock cycles. Accordingly, since the target cannot comply with the data transaction requested in the initial access, it issues a retry 201. This forces the initiator to relinquish the PCI bus (e.g., PCI bus 112) for use by other initiators. The initiator subsequently, arbitrates for and acquires the PCI bus for a second try. The target is still not ready, and thus, issues retry 202, forcing the initiator to again relinquish the PCI bus.
Hence, as shown in process 200, the initiator continually attempts to execute its data transaction, and continually is forced to retry. This process proceeds through the third and fourth try, and their respective retries 203 and 204. After retry 204, the 16 PCI clock cycle latency of the target expires, and finally, the initiator achieves a completed access. However, during the second try, the third try, and the fourth try, the PCI bus is tied up by the initiator and is unavailable to other requesting PCI agents. In this manner, the initiator repeatedly attempting to access the slow target causes a decrease in the availability of the PCI bus with respect to the other PCI agents. This diminishes the total data transfer bandwidth of the PCI bus, and hence, the functionality of the computer system. In addition, since the initiator has no way of knowing when the target will be ready to complete its access, the initiator must continually retry, not knowing when the latency period will expire. This ultimately leads to longer access times for the initiator since each time it attempts to access the target, it must arbitrate for, and be granted, the PCI bus.
Thus, what is required is method and system which minimizes or even eliminates the wasted retry accesses where a faster initiator PCI agent continually attempts to access a slower target PCI agent. The required system should reduce the effective access time for the retrying PCI agents, reducing the effects of repeated access attempts and making the data transaction process with the slower target PCI agent more efficient. The required system should significantly increase the available PCI bus data transfer bandwidth available to other PCI agents. In addition, the required system should provide for the issue of a retry access at an optimal time. The present invention provides a novel solution to the above requirements.